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| www..com Datasheet MLX90255BA Linear Optical Array Features and Benefits 128 x 1 Sensor-Element Organization (1 Not Connected, 1 dummy, 128 real, 1 dummy and 1 Dark Pixel) 385 Dots-Per-Inch (DPI) Sensor Pitch High Linearity and Uniformity for 256 Gray-Scale (8-Bit) Applications High Sensitivity: 1.7V @ 10W/cm @ 0.7ms integration time Special Gain Compensation for use with single LED light source Output Referenced to Ground Low Image Lag Single 5V Supply Replacement for Texas Instruments TSL1301 & TSL1401 and MLX90255AA Operation to 1MHz Applications Position Sensing Electrical Power Assist Steering (EPAS) Spectrometer Applications Ordering Information Part No. MLX90255 MLX90255 Temperature Suffix K K Package LA JA Option -BA -BA Temperature Range -40C to 125C Automotive -40C to 125C Automotive Functional Diagram Description The MLX90255BA linear sensor array consists of a 128 x 1 array of photodiodes, associated charge amplifier circuitry and a pixel data-hold function that provides simultaneous-integration start and stop times for all pixels. The pixels measure 200m (H) by 66 m (W) and 8 m spacing between pixels. Operation is simplified by internal control logic that requires only a serial-input (SI) signal and a clock. The sensor consists of 128 photodiodes arranged in a linear array. Light energy falling on a photodiode generates photocurrent, which is integrated by the active integration circuitry associated with that pixel. During the integration period, a sampling capacitor connects to the output of the integrator through an analog switch. The amount of charge accumulated at each pixel is directly proportional to the light intensity and the integration time. The output and reset of the integrators is controlled by a 132-bit shift register and reset logic. An output cycle is initiated by clocking in a logic 1 on SI. This causes all 132 sampling capacitors to be disconnected from their respective integrators and starts an integrator reset period. (continued on page 4) Page 1 Rev 1.2 08-Aug-01 Pixel 1 Integrator Reset Pixel 2 Pixel 132 VDD 4 Analog OUT External Load 3 Sample Switching Logic Hold Q1 132-Bit Shift Register Q2 Q132 CLK 2 1 5 MLX90255BA Linear Optical Array 3901090255 GND SI www..com Datasheet MLX90255BA Linear Optical Array MLX90255BA Electrical Specifications DC Operating Parameters TA = -40oC to 125oC, VDD = 4.5V to 5.5V (unless otherwise specified) parameter symbol test conditions Min typ max Supply voltage Input voltage High-level input voltage Low-level input voltage Hysteresis on SI and CLK Wavelength of light source Clock frequency Sensor integration time below 60C (1) Sensor integration time (full temperature range) (2) Pixel charge transfer time (full temp range) Setup time, serial input Hold time, serial input (3) Operating free-air temperature Clock pulse duration (high) Clock pulse duration (low) Fclock Tint Tint Tqt Tsu(SI) Th(SI) Ta Tw(H) Tw(L) Vdd Vi Vih Vil 4.5 0 Vdd*0.7 0 0.2 400 64 0.125 0.125 8 350 40 -40 320 320 125 0.4 5 5.5 Vdd Vdd Vdd*0.3 0.8 1000 1024 100 2 units V V V V V nm kHz ms ms s ns ns C ns ns Notes: (1) Reset until clock pulse 18 (on declining flank). Minimum integration time = (133-18) * CLK period + 10s (this is the time the S&H cap needs to follow). At 1MHz clock speed, the minimum integration time becomes 0.125ms. (2) At 125C, the integration time should be limited to 2ms. (3) The SI pulse must go low before the rising edge of the next clock pulse. MLX90255BA Linear Optical Array 3901090255 Page 2 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array MLX90255BA Electrical specifications All tests are made with 0.7ms integration time, at 10mW/cm light = 100% at 25C at 880nm and with a clock speed of 500kHz in, 250kHz out, and 500kHz, unless otherwise specified in the Test Conditions. 100 % light under Test Conditions means that the light is set in such a way that there is 2.4V at the output of the chip. Parameter Symbol Test Conditions Min Typ Max Units Illumination Average analog output (1) Average analog output Average analog output Highest Dark Pixel Non Linearity Pixel Response Non Uniformity (2) Pixel Interaction Test (3) Noise Level (4) Hold spec, same as PRNU Output Settling Time Array Lag (5) Dark Signal Non Uniformity (6) Analog Output Saturation Change in sensitivity with Temperature at 880nm (7) Operating Free Temp Supply Current (8) Idd Illum100 At 25C, 2.4V at output VaoLight At 25C, 100% light Initial offset At 25C, 0% light VaoDark At 125C, 0% light Vaodarkmax At 125C, 0.25ms integration time Nlao1 PRNU PIT Vn PRNUH Ts Alag DSNU All Temp All Temp, 100% light AT 25C All Temp All Temp, 100% light, 62.5kHz All Temp At 25C At 25C At 125C All Temp 0 -40 2 5 0.3 0.5% 4.0% 5% 3 4.0% 450 0.5% 80 140 120 440 3.0 0.8 125 8 6 8.5% 750 11.4 1.5 0 0 14 1.7 0.15 0.40 16 2.1 0.3 1.4 0.8 1.2% 8.5% W/cm V V V V FS FS FS mV (RMS) FS ns FS mV mV V %/C C mA (0) After power on, the first integration scan is not guaranteed correct. This scan is needed for initializing digital levels on chip. After a SI and 133 proper CLK signals, the system is fully initialized and all further scans are valid. The next SI will provide a valid scan. (1) Absolute Light measurements are very test-setup dependent and should be regarded with caution. Relative measurements are possible with 1% accuracy. (2) PRNU is defined as the worst case deviation of any PixelValue (pixel 3 till 130) to the average light value. PixelValue = (Vout of a pixel at 100% light - Vout of same pixel at 0% light) The 90255BA has a cosign shaped gain: external pixels have 15% more gain than middle pixels. (3) PIT = (Vout of pixel 132 @ 10W - Vout of pixel 132 @0W) / (Vaverage @10W - Vaverage @10W) (4) Noise: We compare 5 different measurements, normalize them and then take the RMS value. (5) Array Lag is defined as: (Vaverage 0W 1 Vaverage 0W2) / ((Vaverage 10W Vaverage 0W2). Where 0W1 is a 0% light level, 1ms after a 100% light level. (there can still be some light effects). 0W 2 is a 0% light level, 10ms after a 100% light level, which should be a true dark reference. (6) DSNU is defined as: (max Vout of pixel I @ 0% light) - (min Vout of pixel j @ 0% light) for pixels 3 thru 130 (7) Sensitivity always increases with rising temperature. (8) Idd is measured with Rload disconnected from the output pin. MLX90255BA Linear Optical Array 3901090255 Page 3 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array General Description (continued from page 1) As the SI pulse is clocked through the shift register, the charge stored on the sampling capacitors is sequentially connected to a chargecoupled output amplifier that generates a voltage on the analog output AO. Two dummy pixel values are shifted out first, then the 128 actual pixel bits, followed by two additional dummy pixel bits, for a total of 132 data bits. Although there are only 132 pixels, 133 clock pulses are necessary for a complete shift out. The final pulse is used to re-initialize the shift register. The integrator reset period ends 18 clock cycles after the SI pulse is clocked in. So the lightintegration starts after the 18th CLK pulse. The light-integration ends at the next SI pulse. Between the end of the 133th clock pulse and the next SI pulse, a minimum time of 10s is necessary for an effective S&H function. So the minimum integration time of the MLX90255BA is (133 -18) * Ts + 10s and thus dependent on clock speed. (Ts = clock period) After the 132 data bits are clocked out, the output becomes high impedance. (see figure) The AO is driven by a source follower that requires an external pulldown resistor. (typically 330) The output is nominally 125mV for no light input and 2.4V for a nominal full-scale output. The pixel gain is 15% bigger at the edges than in the middle (cosine correction) in order to get a flat output when illuminating the device with a single LED light source. The MLX90255BA is intended for use in a wide variety of applications, including: image scanning, mark and code reading, optical character recognition (OCR) and contact imaging, edge detection and positioning, and optical linear and rotary encoding. The MLX90255BA is a replacement for the Texas Instruments' TSL1301 and TSL1401 parts. Absolute Maximum Ratings Supply Voltage, Vdd Digital Input Current Range Operating Free-Air temperature range, Ta Storage temperature range, Tstg Lead Temperature 1.6mm (1/16 inch) from case for 10 seconds Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated under "recommended operating conditions" is not implied. Exposure to absolute-maximum -rated conditions for extended periods may affect device reliability. +7V -20 to 20 mA -40C to 125C (automotive compliant optical package) -40C to 125C 260C MLX90255BA Linear Optical Array 3901090255 Page 4 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array Performance Graphs Typical Photodiode Spectral Response Curve (%), without Anti Reflection Coating* *There is also an option for an Anti Reflection Coating . This will remove the interference ripples in the figure above. With this special Anti Reflection Coating, the sensitivity curve in function of wavelength will be somewhat lower (typically 4%) but will no longer display interference ripples. MLX90255 Timing Diagram MLX90255BA Linear Optical Array 3901090255 Page 5 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array Disclaimer Melexis reserves the right to periodically make modifications to product specifications. The information included herein is believed to be accurate and reliable. However, Melexis assumes no responsibility for its use; nor for any infringements of patents or other rights of third parties which may result from its use. Melexis MLX90255BA Linear Optical Array 3901090255 Page 6 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array MLX90255BA (SMD8) LA package dimensions 8 7 6 5 1 2 3 4 MLX90255BA Linear Optical Array 3901090255 Page 7 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array LA (SMD8) Pin Description Pin 1 2 Symb ol SI CLK Description Serial Input. Si defines the start of the data-out sequence Clock. CLK controls the charge transfer, pixel output and reset (together with SI) Analog Output Supply voltage, for both analog and digital circuits Ground (substrate). All Vss Pins are referenced to the substrate. 3 4 5, 6, 7, 8 A0 Vdd Vss Note: All 4 Vss pins are internally connected to form a large ground plane to get better EMC characteristics. MLX90255BA (GLP5) JA package dimensions 1 2 3 4 5 QS9 MLX90255BA Linear Optical Array 3901090255 Page 8 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array JA (GLP5) Pin Description Pin 1 2 Symb ol SI CLK Description Serial Input. Si defines the start of the data-out sequence Clock. CLK controls the charge transfer, pixel output and reset (together with SI) Analog Output Supply voltage, for both analog and digital circuits Ground (substrate). All Vss Pins are referenced to the substrate. 3 4 5 A0 Vdd Vss MLX90255BA Linear Optical Array 3901090255 Page 9 Rev 1.2 08-Aug-01 www..com Datasheet MLX90255BA Linear Optical Array MLX90255BA Leadframes JA (GLP5) Leadframe LA (SMD8) Leadframe For the latest version of this document, go to our website at: www.melexis.com Or for additional information contact Melexis Direct: Europe and Japan: Phone: +32 13 61 16 31 E-mail: sales_europe@melexis.com All other locations: Phone: +1 603 223 2362 E-mail: sales_usa@melexis.com QS9000, VDA6.1 and ISO14001 Certified MLX90255BA Linear Optical Array 3901090255 Page 10 Rev 1.2 08-Aug-01 |
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